1. Field of the Invention
The present invention relates to an internal voltage generation circuit, and particularly to an internal voltage generation circuit capable of generating a voltage at a desired level regardless of the operation environment. More particularly, the present invention relates to an internal power supply circuit with reduced power consumption in a standby state for a semiconductor integrated circuit employed in portable equipment.
2. Description of the Background Art
In portable equipment, various semiconductor integrated circuit devices are used. Static random access memories (SRAMs) are widely used as memory devices in such portable equipment. As the SRAM consumes a low power supply current generally equal to or less than 1 SEA in the standby state, battery driving which is necessary character for portable equipment, can be readily realized. High densification and large scale integration have been progressed to implement an SRAM with high performance and reduced cost. With the high densification/large scale integration progressed, however, a transistor element is miniaturized and breakdown voltage thereof lowers. To prevent dielectric breakdown caused by the reduced breakdown voltage, power supply voltage must be lowered. In a practical system where semiconductor integrated circuit devices are used, however, a wide variety of components are employed and the power supply is generally provided common to all the components. Therefore, it is difficult to alter the power supply voltage, considering the requirement only for the SRAM. Thus, there is a need for a power supply circuit generating a power supply voltage at a lower level in the SRAM without changing a level of the power supply voltage supplied from a source external to the SRAM.
FIG. 21 shows an example of a structure of a conventional internal power supply circuit. In FIG. 21, an SRAM 1 includes a load circuit 5 having peripheral circuitry and a memory array, and an internal power supply circuit 10 supplying an operating power supply voltage to load circuit 5. Load circuit 5 operates receiving a power supply voltage Vo from internal power supply circuit 10 as one operating power supply voltage Vcco. Load circuit 5 also uses ground voltage on a ground node 6 as another operating power supply voltage. A battery 9 supplies power supply voltage to the SRAM.
Internal power supply circuit 10 includes a reference voltage generation circuit 2 generating a reference voltage Vref at a fixed level independent of the power supply voltage (hereinafter referred to as an external power supply voltage) supplied from a source external to SRAM 1, a differential amplifying circuit 3 comparing power supply voltage Vo on an internal power supply line 8 and reference voltage Vref and supplying an output signal according to the result of the comparison, and a current drive transistor 4 connected between a power supply node 7 and internal power supply line 8 and having its conductance controlled by the output signal from differential amplifying circuit 3. Battery 9 applies the voltage on power supply node 7. Current drive transistor 4 is constituted of a p channel MOS (insulated gate type field effect) transistor.
In operation, differential amplifying circuit 3 supplies as an output a signal thereof according to the difference between power supply voltage Vo on internal power supply line 8 and reference voltage Vref. When the level of power supply voltage Vo is higher than that of reference voltage Vref, differential amplifying circuit 3 supplies an output signal at an H (logical high) level, turning current drive transistor 4 to an off-state. Conversely, if the level of power supply voltage Vo is lower than the level of reference voltage Vref, differential amplifying circuit 3 supplies an output signal at a low level according to the difference, hence conductance of the current drive transistor increases and current flows from power supply node 7 to internal power supply line 8, whereby the level of power supply voltage Vo is raised. Thus internal power supply circuit 10 maintains the level of power supply voltage Vo on internal power supply line 8 at the level of reference voltage Vref.
In internal power supply circuit 10, power supply voltage Vo is not generated directly through differential amplifying circuit 3 but through current drive transistor 4 according to the output signal from differential amplifying circuit 3. In other words, current drive transistor 4 acts as a buffer driving internal power supply line 8 according to the output signal of differential amplifying circuit 3, and equivalently increases the current drivability of differential amplifying circuit 3. Differential amplifying circuit 3 and current drive transistor 4 have such current drivability as to prevent the level of power supply voltage Vo from being lowered, even when load circuit 5 operates and consumes power supply current of about a few tens mA.
In the internal power supply circuit shown in FIG. 21, through the adjustment of characteristic values of elements included in reference voltage generation circuit 2 with laser trimming or the like, precise setting of the level of reference voltage Vref, or the level of power supply voltage Vo can be achieved. As well known, however, in differential amplifying circuit 3, current is supplied from a current mirror circuit to a comparison stage, and the voltage level and response speed of the output signal are determined by the current amount. Therefore, in differential amplifying circuit 3, a relatively large power supply current (current flowing from the power supply node to the ground node of differential amplifying circuit 3) of about a few .mu.A flows, thereby causing a problem of large current consumption in the standby state. Unlike a DRAM (Dynamic Random Access Memory), in the SRAM, at the activation of a chip select signal or a chip enable signal, a row and a column are simultaneously selected inside. If differential amplifying circuit 3 is maintained in an inactive state during the standby, the activation of differential amplifying circuit 3 is delayed at the start of an active cycle (memory cell selection operation cycle), and decrease in operating power supply voltage Vcco of load circuit 5 caused by a leakage current in a standby cycle cannot be compensated for, whereby a stable operation cannot be secured. Therefore the operation of differential amplifying circuit 3 cannot be stopped simply in the standby.
FIG. 22 represents another structure of the conventional internal power supply circuit. In FIG. 22, an internal power supply circuit 10 includes a high resistance element 11 connected between a power supply node 7 and a node 14, and n channel MOS transistors 12-1.about.12-6 connected in series between node 14 and a ground node 6. These n channel MOS transistors 12-1.about.12-6 each have a gate and a drain connected together.
Internal power supply circuit 10 further includes a current drive transistor 13 constituted of an n channel MOS transistor causing a current flow from power supply node 7 to an output node 15 according to a voltage on node 14 to generate an output voltage Vo. The resistance value of high resistance element 11 is set sufficiently higher than a channel resistance (on resistance) of MOS transistors 12-1.about.12-6. Therefore, these MOS transistors 12-1.about.12-6 each operate in a diode mode and cause a voltage drop of threshold voltage VTN. Thus, voltage V14 at node 14 is represented by the following equation. EQU V14=6.multidot.VTN
MOS transistor 13 operates in a source follower mode because the level of its gate voltage is lower than voltage level on a drain node.
Therefore the level of output voltage Vo on output node 15 is lower than the level of voltage V14 on node 14 by threshold voltage VTN of MOS transistor 13. Thus, output voltage Vo is represented by the following equation. EQU Vo=V15=V14-VTN=6-VTN-VTN=5.multidot.VTN
When threshold voltage VTN is 0.7 V, output voltage Vo is 3.5 V.
In the structure of internal power supply circuit 10 shown in FIG. 22, the power supply current is determined by the resistance value of resistance element 11. The resistance value of resistance element 11 can be increased substantially without limitation (the power supply current can be reduced to a current value of the order of pA as it is used only for compensating for leakage current at PN junctions of MOS transistors 12-1.about.12-6). Thus the power supply current can be easily set equal to or less than 1 .mu.A, which is a requirement for standby leakage current in the SRAM, whereby reduced power consumption in the standby state is achieved.
Threshold voltage VTN, however, has temperature dependency of about 2 mV/.degree. C. and varies by 0.1 to 0.2 V chip by chip due to fluctuation of manufacturing parameters. As output voltage Vo is given by an integer multiple of the threshold voltage VTN, temperature dependency and variations are also amplified. In the structure of FIG. 22, the variation is about 1 V, and in practice, output voltage Vo cannot be generated at a correct level.
The problem of the internal power supply circuit as described above is also encountered in a circuit generating an internal voltage at a predetermined level such as reference voltage.